The present invention relates to a microprocessor capable of operating a particular circuit block at high speed without increasing a consumption power.
Various techniques of reducing the consumption power of a microprocessor have been proposed. For example, as disclosed in JP-A-8-272579 xe2x80x9cVariable Clock Generatorxe2x80x9d, most of conventional techniques intend to reduce the consumption power of a microprocessor by lowering the frequency of a clock to be supplied to a unit not requiring a high speed operation among a plurality of units constituting the microprocessor. Lowering the clock frequency corresponds to lowering an operation ratio (activation ratio) of CMOS circuits because most of microprocessors are made of CMOS circuits. This method is therefore effective for lowering the consumption power.
Recent developments on multimedia fields are remarkable. Microprocessors suitable for multimedia are highly desired. Such a microprocessor is required to execute a complicated process such as graphics and image processing at high speed. There is a recent tendency that a higher frequency is used as the machine clock of a microprocessor. With a higher clock frequency, the consumption power increases. Reducing the consumption power of a microprocessor is an important issue.
Recently, there are many microprocessors prevailing to general homes, such as microprocessors for a digital TV and a game machine. Such microprocessors are required and expected to use inexpensive packages for low cost purposes and to be resistant against a use in a windless state. In order to meet such expectation, a low consumption power of a microprocessor is particularly necessary.
There are high market needs for a high performance and a low consumption power of microprocessors, particularly microprocessors for multimedia fields. However, although conventional techniques can reduce the consumption power of a microprocessor, they do not consider both the reduction in the consumption power and the improvement on the performance.
It is an object of the invention to solve this problem and provide a microprocessor capable of improving the performance of the microprocessor without increasing the consumption power.
According to the invention, one of a plurality of power supply voltages having different values and one of a plurality of clocks having different frequencies are selectively supplied to each of a plurality of circuit blocks constituting a microprocessor, in order to change the operation speed of a specific circuit block to a higher operation speed. A clock having a higher frequency is called, hereinafter where appropriate, a high speed clock.
Most microprocessors are made of CMOS circuits. In general, the highest operable frequency of logical circuits such as CMOS circuits increases approximately in proportion to a power supply voltage supplied to the circuits. In order to drive a CMOS circuit at a high speed clock, it is therefore necessary to supply a higher power supply voltage. From this reason, the invention utilizes a plurality of power supply voltages. The frequency of each of a plurality of clocks and the value of each of a plurality of supply voltages are selected so that the highest speed clock having a highest frequency among the plurality of clocks can be used by a circuit block supplied with the highest power supply voltage among the plurality of power supply voltages and that one of clocks slower than the highest speed clock can be used by a circuit block supplied with one of power supply voltages lower than the highest power supply voltage. The circuit block supplied with the highest power supply voltage is made of circuit components having a breakdown voltage higher than the highest power supply voltage so that the circuit block can operate normally at the highest power supply voltage.
The invention not only realizes a high speed operation of a microprocessor but also reduces the consumption power. Generally, the consumption power of a logical circuit such as a CMOS circuit is proportional to the operation frequency of the circuit and to the square of a power supply voltage supplied to the circuit. Accordingly, in this invention, the number of circuit blocks supplied with both the highest power supply voltage and highest speed clock is limited.
More specifically, the invention provides:
a power supply circuit for selectively supplying one of a plurality of power supply voltages having different values to each circuit block;
a clock supply circuit for selectively supplying one of a plurality of clocks having different frequencies to each circuit block; and
a control circuit for instructing said power supply circuit and said clock supply circuit to selectively supply a clock and a power supply voltage to each circuit block.
When the highest speed clock and highest power supply voltage are supplied to one of the circuit blocks, the control circuit controls to supply one of clocks slower than the highest speed clock and one of power supply voltages lower than the highest power supply voltage to at least one of other circuit blocks.
More specifically, when a clock supplied to at least one of the plurality of circuit blocks is changed to a faster speed clock, a clock supplied to at least one other of the plurality of circuit blocks is changed to a slower speed clock.
In this manner, an increase in the consumption power of one circuit block operating at a higher operation speed is compensated by a reduction in the consumption power of the other circuit block. The total power consumption of the microprocessor can therefore be suppressed lower than a predetermined maximum consumption power.
Using both a high speed clock supplied to one circuit block and a low speed clock supplied to another circuit block can be applied to various modes.
For example, a circuit block can operate at a higher speed than that in a normal operation mode. In this case, a clock higher than that in the normal operation mode is supplied to the circuit block. If necessary, a higher power supply voltage is supplied to the circuit block. For example, if the faster clock is the highest speed clock, the highest power supply voltage is supplied to the circuit block. In this manner, the operation speed of the circuit block is raised. In this case, the clock supplied to one of other circuit blocks is changed to a lower speed clock than that in the normal operation mode.
Alternatively, a circuit block driven by a lower speed clock than the highest speed clock can be driven at the highest speed clock. In this case, the clock supplied to another circuit block is changed to a lower speed clock. For example, if there is a circuit block supplied with the highest speed clock before the clock change, the clock supplied to the circuit block is changed to a lower speed clock.